Lowest Latency with the Highest Bandwidth
by Nick Schwartzman Samsung Semiconductor, Inc.
Courtesy: Samsung Semiconductor, Inc.
DRAM performance is measured with two metrics: bandwidth and latency. Surprisingly, one type of DRAM delivers the highest performance in both areas – the Rambus® DRAM. It is widely recognized that with the availability of the 1.6 gigabyte per second Rambus DRAM (RDRAM®), sustainable system bandwidth has jumped a factor of 10 over SDRAM. What hasn’t been as apparent is that RDRAM latency has also been improved relative to SDRAM. What may be even more surprising is that 133 MHz SDRAM latency is worse than PC100 SDRAM.
How is component latency defined? The accepted definition of latency is the time between the moment the RAS (Row Address Strobe) is activated (ACT command sampled) to the moment the first data bit becomes valid. Synchronous device timing is always a multiple of the device clock period.
The fundamental latency of a DRAM is determined by the intrinsic speed of the memory core. All commodity DRAMs use the same memory core technology, so all DRAMs are subject to the same intrinsic latency. Any differences in latency between DRAM types are therefore only the result of the differences in the speed of their interfaces.
At the 800 MHz data rate, the interface to a Rambus RDRAM operates with an extremely fine timing granularity of 1.25 ns, resulting in a component latency of 38.75 ns. The PC100 SDRAM interface runs with a coarse timing granularity of 10 ns. Its interface timing matches the memory core timing very well, so that its component latency ends up to be 40 ns. The 133 MHz SDRAM interface, with its coarse timing granularity of 7.5 ns, incurs a mismatch with the timing of the memory core which increases the component latency significantly, to 45 ns.
|The Rambus DRAM has the highest bandwidth and the lowest latency|
The latency timing values can be computed easily from the device data sheets. For the PC100 and 133 MHz SDRAMs, the component latency is the sum of the tRCD and CL values. The RDRAM’s component latency is the sum of the tRCD and TCAC values, plus one half clock period for the data to become valid.
Although component latency is an important factor in system performance, system latency is even more important, since it is system latency that stalls the CPU. System latency is determined by adding external address and data delays to the component latency. For PCs, the system latency is measured as the time to return 32-bytes of data, also referred to as the “cache line fill” data, to the CPU.
|Rambus Memory has the lowest system as well as the lowest component latency|
In a system, SDRAMs suffer from what is known as the two-cycle addressing problem. The address must be driven for two clock cycles (20 ns at 100 MHz) in order to provide time for the signals to settle on the SDRAM’s highly loaded address bus. After the two-cycle address delay and the component delay, three more clocks are required to return the 32 bytes of data. The system latency of PC100 and 133 MHz SDRAM adds five clocks to the component latency. The total SDRAM system latency is 90 ns for PC100 and 75 ns for 133 MHz SDRAM.
The superior electrical characteristics of a Rambus system eliminate the two-cycle addressing problem, requiring only 10 ns to drive the address to the RDRAM. The 32 bytes of data stream back to the CPU at 1.6GB/second, which works out to be 18.75 ns. Adding in the component latency, the RDRAM system latency is 70 ns, significantly faster than both PC100 and 133 MHz SDRAM.
Measured at either the component or system level, Rambus DRAMs have the fastest latency. Surprisingly, due to the mismatch between its interface and core timing, the 133 MHz SDRAM is significantly slower than the PC100 SDRAM. The RDRAM’s low latency coupled with its 1.6 gigabyte per second bandwidth provide the highest possible sustained system performance.
We would like to take this opportunity to thank Nick Schwartzman and Samsung Semiconductor, Inc. for providing this very informative information.
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