Memory, Evolution or Revolution?

Evolution or Revolution?


A little more than two years ago, JEDEC SDRAM was perceived as having a theoretical design limitation of 125 MHz, although engineers thought that technology advances may enable manufacturers to push this number up to 133 MHz operation. Obviously the engineers were able to refine SDRAM technology and squeeze out better performance, as PC 133 was introduced a short time thereafter along with some SDRAM modules able to repeatedly reach 150 MHz to 200 MHz. The historical issues here are important though, if for no other reason than to demonstrate the speed in which technology advances are taking place. Given that motherboard chipsets were undergoing complete redesigns to accommodate the release of faster and faster processors, technology had to make a concerted effort to reduce latency and find more memory bandwidth to keep up.

During 1998 there were several competing new standards on the horizon that looked very promising, however most of them required special pin-outs, smaller bus widths along with a multitude of other design considerations. Not withstanding the fact that SDRAM still had its perceived limitations, the theoretical Double Data Rate SDRAM looked very appealing, as did DRDRAM (Rambus). Early on, this new DDR SDRAM design allowed the activation of output operations on the chip to occur on both the rising and falling edge of the clock cycle. This promised improved latency, but wasn’t doing much for bandwidth. At the time only the rising edge could signal an event to occur, so the theoretical DDR SDRAM design should effectively double the speed of operation up to at least 200 MHz.

As a side note, there are already two or three Socket 7 chipsets that support DDR SDRAM, as well as one or two VIA chipset based motherboards and at least one Intel chipset based motherboard that have been advertised as supporting DDR SDRAM. Obviously, more will certainly follow given the fact that memory manufacturers have decided to make this memory available in limited quantities by year end 2000, and into industry wide distribution by Q2 of 2001. Looking at Rambus versus DDR, in this industry, many times it is the first to market that gains the support, rather than the best technology.

DDR (Double Data Rate) memory is the next generation SDRAM, and like its predecessor, DDR is synchronized with the system clock. The biggest single difference between DDR and SDRAM memory is that DDR reads data on both the rising and falling edges of the clock signal. SDRAM only carries information on the rising edge of a signal. Basically this allows the DDR module to transfer data twice as fast as SDRAM. For example, instead of a data rate of 133 MHz, DDR memory transfers data at 266 MHz. Referring back to the historical perspective, as you can see, in a relatively short length of time, technology advances found a way to overcome the perceived SDRAM limitation.

DDR modules, like their SDRAM predecessors, are called DIMMs. They use motherboard system designs similar to those used by SDRAM, however DDR is not backward compatible with and cannot be used in SDRAM designed motherboards. DDR memory supports both ECC (Error Correction Code) and non-ECC (non-error correcting code).

Here’s an example of an SDRAM DIMM module.

Here’s an example of the new DDR SDRAM DIMM module.

As you can see, the modules are nearly identical (but not quite).

Enhanced DDR-II

With all of the advancements in processor speeds, as well as those in memory technology, latency issues continue to grow in proportion to the advances and are becoming even greater issue. Continued processor, motherboard chipset and memory testing seems to suggest that higher bandwidth is more important than peak bandwidth in overall system performance. Increasing device densities demands that power and memory refresh and overhead issues be addressed if memory makers really intend to meet their quest for the next generation of DRAM.

Another proposed standard currently evolving at JEDEC is that of DDR-II, or Enhanced DDR-II. Enhanced Memory Systems (Ramtron), working with JEDEC, AMI2, and other industry experts has proposed a simple low latency core architecture for the DDR-II SDRAM that addresses both peak and effective bandwidth to incorporate the best of both worlds.

Enhanced Memory Systems states that Enhanced DDR-II is fully compatible with the current DDR-II proposal, and in fact it is being proposed as a performance enhancement that has identical pin-outs, the same command table, the same number of banks, the same mode registers, and the same DRAM core timings. It is said the integration of a page wide row cache per bank reduces average latency by allowing direct cache access on page hits while closing the DRAM bank as early as possible to reduce subsequent page miss latency. Precharge and refresh rates are accomplished while simultaneously bursting data out of the cache, resulting in higher performance and lower refresh overhead.

Memory latency leads to increasing amounts of processor idle time. If the memory latency remains unchanged, the number of cycles of processor time is doubled with each doubling of the speed of the processor. Obviously, the solution would be to develop a new memory technology that would lead to memories with much lower inherent latency than present ones, thereby resolving the problem at the source. 

Protocol Based DRAM (SyncLink DRAM, renamed SLDRAM)

We’re not going to spend too much time with SLDRAM, as it now seems as though it is a dead issue. We felt, however, that you should know something about its history should the acronym be bantered about. Most of the previously discussed DRAM have separate address, data and control lines which limits the speed at which the devices can operate with current technology. The memory industry, in an attempt to overcome this limitation, began examining several designs that would implement all of these signals on the same bus. Two of these protocol based designs that received most of the industry’s attention over the last three years or so were SyncLink DRAM (now called SLDRAM) and Direct Rambus DRAM (DRDRAM) licensed by Rambus, Inc.

History, the short version: In 1995 memory makers perceived that Intel already had a corner on both the processor and motherboard chipset markets, and was now attempting to corner the memory market as well. As we all should know by now, any cornering of the electronics and/or computer technology markets is short-lived at best, but nevertheless, that was the perception of the moment. To alleviate this perceived threat and to try and develop around the current DRAM limitations, some of the memory makers hurriedly formed an alliance in 1995 to research and develop an ad hoc specification for a Rambus-like architecture. In doing so, these memory makers formed SyncLink Corporation within the SCIzzL Association at Santa Clara University. Over the course of the following two years, the new standard was being developed and was being referred to initially as Synclink DRAM.

Aside from the ongoing development of a new standard, a trademark infringement issue arose between SyncLink Corporation and MicroGate Corporation over the use of the SyncLink name. In January 1998, SyncLink Corporation announced that it was reforming under SLDRAM, Inc. And lest we forget, some of the major sponsor/partners involved in this development effort included Apple Computer, Fujitsu Ltd., Hewlett-Packard Company, Hitachi Ltd., Hyundai Electronics Industries Co., Ltd., IBM Microelectronics, IBM World Procurement, LG Semicon Co., Ltd., Matsushita Electric Co., Micron Technology, Mitsubishi Electric Corp., MOSAID Technologies, Mosel-Vitelic, Motorola, NEC Corporation, Nippon Steel Corp., Oki Electric Industry Co., Ltd., Samsung Electronics Co., Ltd., Siemens, Texas Instruments, Inc., Toshiba Corp., Vanguard International Semiconductor, VLSI Technology.

In mid-1997, memory chip makers were up in arms about the deal between Rambus and Intel, and were claiming that Intel was again making an attempt to corner the memory market, as it had allegedly attempted to do in late 1995. Memory chip makers felt that Intel was locking them out of the specification development in such a way that Intel could bring high performance Rambus based systems onto the market before its competitors could get hold of the specifications. In an over simplification, Rambus is essentially command driven smart memory that coordinates with the CPU more cooperatively than old fashioned dumb memory. Intel’s argument was that this type of memory design was necessary in high-speed, high-end, work stations, but the memory makers saw this as just another marketing strategy rather than a technology advance.

To counter the revived threat, in January of 1998 memory chip makers redoubled their efforts to promote synchronous link DRAM (SLDRAM) as an alternative to double-data-rate (DDR) and Direct Rambus DRAM by joining the newly formed SLDRAM, Inc.. This new entity was to be a stand-alone, nonprofit corporation, with an independent charter to pursue new memory chip architectures. To digress for a moment, in April of 1997, Siemens had announced the development of the first SLDRAM, based on technology jointly developed by Siemens, IBM, and Toshiba. In September 1997, the SLDRAM consortium released specifications for its first reference devices.

In April of 1998 Micron Technology Inc. released engineering samples of its new SLDRAM to the PC industry in an attempt to spark some interest. Under the perceived threat from Intel, Micron felt that SLDRAM held promise and even went so far as to say that high-performance OEMs were already accustomed to working with independent chip set suppliers, and Micron expected that they would be responsive to the SLDRAM chip sets, especially if they are first to market. In an ambitious statement, Micron’s Gene Cloud, presuming that Intel would not support any memory type other than Direct RDRAM, stated that “If DRDRAM falters in any way, you can be sure Intel will quickly change course on wideband high-speed memory”. If he only knew how truthful those words were at the time!

Nearly a year later though, the music died. In April of 1999, most of the major memory makers essentially abandoned SLDRAM, Inc., and joined a new effort to promote double-data-rate (DDR) DRAM, Advanced Memory International Inc. (AMI2). This new entity grew out of the remains of SLDRAM Inc., which quietly faded into the darkness after trying to promote the SLDRAM format. It has been said that while AMI2 is not technically an offshoot of SLDRAM Inc., it has adopted its bylaws and functional framework. Members include Fujitsu Ltd., Hitachi Ltd., Infineon Technologies AG, Micron Technology Inc. and Mitsubishi Electric.

The group’s primary goal is to advance DDR memory while pushing for a plan for the architecture’s next generation, DDR-2 DRAM. It is said that systems with DDR-2 chips would be available in two years, sometime around Q4 of 2001, and that the designs will offer data-transfer rates of up to 4 Gb per second, effectively doubling the bandwidth of existing DDR devices. DDR-2 uses the memory-cell designs seen in both standard SDRAM and DDR DRAM chips, but it will feature some I/O designs to facilitate faster data rates. The architecture will be offered as an open standard to the DRAM industry.


Until recently, Intel has placed their money on the proprietary memory design developed by Rambus, Inc. On the surface, Rambus looked to be the fastest solution for system memory due to its operational speeds up to 800MHz. Unfortunately though, the design is only up to twice as fast as current SDRAM operation due to the smaller bus width, 16 bits as opposed to 64 bits. Although this is not necessarily a problem in high-end work stations, there are some potentially serious issues which need to be addressed with this technology.

Higher speeds require short wire lengths and additional shielding to prevent problems with EMI. In addition, with early Rambus designs, especially the 600 MHz and 700 MHz designs, latency times are actually worse than currently available fast SDRAM. Since most of today’s desktop user applications do not actually utilize the full bandwidth of the memory bus, simply increasing the bandwidth while ignoring latency issues will not provide the expected performance improvements. Processors operating with 800MHz bus speeds will certainly require more than double the current memory bandwidth.

While these issues are somewhat serious for low-end work stations (those implementing the i820 chipset), when Rambus is implemented on high-end work stations, such as those implementing processor speeds of 733 MHz and greater on motherboards built around the I840 chipset, these problems do not seem apparent. Unfortunately though, up until recently the biggest drawback to Rambus was its proprietary technology. Several months ago several pundits were suggesting that manufacturers wishing to implement a solution with DRDRAM were going to be required to pay an endless royalty to Rambus, Inc., and would have no real control over the technology. Obviously at the time, this was not at all appealing to most memory manufacturers.

With all of the controversial comparisons of Rambus as opposed to DDR SDRAM (and now DDR-II), along with the new Itanium chipset designs and processors surpassing the 1.5 GHz mark, even Intel is looking to move onto other technologies. In a news byte released October 30, 2000 by Jack Robertson, of EBN., ( Intel roadmap shows little Rambus support in 2001 ), he discusses the fact that Intel’s most recent roadmap shows little support for Rambus. According to this alleged confidential document acquired by Electronic Buyer’s News, it shows Intel dropping Direct Rambus DRAM from every computing platform but high-end workstations by mid-2001.

According to the document, Intel will phase out the slow selling Direct RDRAM enabled 820 chipset in the first quarter of next year, while the soon to be released Intel 850 chipset will be dropped in the middle of the third quarter of 2001 in favor of two new chipsets known as Almador and Brookdale, which are slated to be introduced in the middle of next year. Both are said to support single-data-rate and DDR capability. At that time, Intel’s sole remaining Rambus chipsets will be the i840 and the enhanced 850 device code-named Tehama-E, which the company is rolling out for workstations and PCs costing more than $2,000. Maybe it wasn’t Rambus that turned Intel off with its I820 chipset, but rather the fact that is has been continually plagued by problems. Is Rambus dead? On to the summary..

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