Determining the application speed of SDRAM Modules
Since the publication of our memory resources pages some 15 months ago, we have been getting an ever increasing number of inquiries from computer users repeatedly asking how they would go about determining whether or not their memory modules are actually PC-100 compliant? In an effort to answer some of these questions, address other memory related issues, and provide a non-technical approach to the PC-100 Standard, we have constructed a number of web pages in the Performance Center and Technical Center sections of our website devoted entirely to memory issues. We’ll begin this aspect of our review with two illustrations of PC-100 compliant memory modules, one from Micron-Crucial and another from Samsung. These would be the same type of modules the average consumer would see when purchasing them. Obviously, without the right tools and some knowledge, it’s extremely difficult to determine what the information on these modules mean. Let’s move on and see what it does mean!
All DRAM memory that has a synchronous interface is known generically as SDRAM. This includes CDRAM (Cache DRAM), RDRAM (Rambus DRAM), ESDRAM (Enhanced SDRAM) and others, however the type that is most often referred to merely as SDRAM is, in reality, JEDEC standard synchronous DRAM. JEDEC developed the specification for SDRAM. The PC-100 Standard was developed by Intel, in conjunction with major memory manufacturers, to accomplish, among other things, an assurance of data integrity at higher system speeds. There is no question that, due to an overall lack of understanding of the requirements set forth in that standard, many vendors and resellers are selling memory labeled as PC-100 that really doesn’t meet Intel’s PC100 specification. We mentioned the JEDEC specification above to raise an important point.
According to some engineering consultants, current industry practices do not provide a method for ensuring module clock timing accuracy especially for PC100, PC133 and DDR:
- The JEDEC DIMM Clock delay spec is said to be incorrect on the theory that .6ns is not possible, and no measurement method has been specified. (We disagree with this statement.)
- The Intel specifications, while defining the clock structure accurately and in detail, provide no measurement method or delay value (at DIMM-level).
- Alleged ‘PC100 or PC133-compliant’ DIMMs, from major suppliers, may vary by greater than 1ns (10% of the entire cycle time) in clock arrival at SDRAM.
- Since there is no standard delay measurement solution, system manufacturers have selected their own various clock delay measurement solutions or specifications, driving suppliers to have inconsistent clock delays.
- With the ever increasing SDRAM clock speeds, such as with PC-133 and DDR DIMMs, improved clock definitions and measurement techniques are required.
Engineers from IBM, and memory chip manufacturers in general, have been working with engineers from computer manufacturers in an effort to define a consistent measurement tool to ensure that PC-133 and DDR (SDRAM generally) product standards will be met. In order to further develop “the standard” and tolerances for their PC-133 and DDR enabling efforts, a two-pronged approach was taken:
- Define ‘reference’ nets for all new module standards. ‘Reference’ nets must permit both simulation and subsequent hardware validation.
- Define a ‘Clock Reference Board’, which can serve as a test vehicle for Module producers (to ‘tune’ the module assembly during validation and a qualification vehicle for system producers.
So, as you can see, while their are very tight specifications and extremely restrictive standards, DRAM manufacturers can easily misinterpret them, sometimes intentionally. Don’t be misled by this information though, SDRAM can be manufactured to meet the present standards and specifications, however doing so may be somewhat expensive early on, which gives rise to some not so scrupulous manufacturers and vendors releasing SDRAM that is not ‘qualified”.
Earlier, when we discussed the testing and performance problems we experienced with vendors and resellers, one of the first problems that we noticed was that in all but one case, both the sales people and the technicians had no real technical background and most did not know what various memory related terms such as RAS, CAS, latency, access time, data bit, ECC, refresh and burst meant.
The PC-100 Standard is quite a thorough and technical publication, so let’s see if we can reduce it to plain and simple terms that just about everyone can understand. Intel, in publishing these manufacturing standards, admitted that meeting them would pose some significant challenges for semiconductor manufacturers, memory module manufacturers and resellers. And yes, there is a difference. In some cases the memory module manufacturer is not the manufacturer of the actual semiconductor (chip). In later comments added by Intel, it admitted that at 100MHz speeds, their timing specification is so tight that every aspect of the memory bus, from trace lengths and impedance, all the way to the alignment of the PC board layers, must be perfect.
Unfortunately, merely following or meeting the PC-100 Standard may not be enough! This is due to both the intricate manufacturing and testing procedures of PC-100 SDRAM as well as the fact that each PC-100 compliant SDRAM module must use SDRAM chip specifications at 8ns (nanoseconds) or better, with internal frequencies of at least 125Mhz. The information below, from Samsung and Micron-Crucial, demonstrates this.
|Micron SDRAM Module Designators|
|Micron P/N||Marked Speed||CAS Latency||Bus Speed|
|Samsung SDRAM Module Designators|
|Samsung P/N||Marked Speed||CAS Latency||Bus Speed|
You can review more about memory related issues by following these links, such as Memory Speed, overall Memory Latency and CAS Latency.
Let’s dissect a PC-100 compliant memory module
Or click here to go to the Performance Center Home Page
This page updated: 11/01/2000